The present invention relates to a surge voltage suppressed power inverter using a voltage driven switching element such as a MOS transistor and the like.
Various circuits have been practically used as a power inverter using a semiconductor element.
Recently, IGBTs or MOSFETs which can be switched at high speeds have been used as switching elements for the power inverter.
Since the MOS transistors and IGBTs have a high switching speed, the rate of changes in current di/dt and the rate of changes in voltage dv/dt is so high that surge current due to parasitic inductance is very high. Exceeding of the surge voltage beyond the maximum rating of the switching element may cause damages to the element. Accordingly, various surge protection circuits are used.
An example of prior art surge voltage suppressing means is described in JP-A-9-139660. A series circuit of a capacitor and resistor is connected between the collector and emitter of an IGBT in parallel. A diode is connected in parallel with the resistor. This circuit is referred to as a xe2x80x9csnubber circuitxe2x80x9d. Since the circuit is arranged to absorb surge voltage per se by the capacitor, there occurs problem as follows: Firstly, since the capacitor will have higher impedance at low frequencies, sufficient surge suppression is not attained for a surge voltage having a wide time width. Secondly, since the capacitance which is necessary for the capacitor increases in proportional to the parasitic inductance and the square of the cut-off current if the voltage to be absorbed is assumed as constant, a capacitor having a high capacitance higher than the order of several xcexcF and high breakdown voltage is necessary. Since such a capacitor is high in price and large in size, this is an obstacle for reduction of the power inverter in size and cost. Thirdly, the power loss of the resistor increases in proportional to the parasitic inductance and the square of the cut-off current if the switching frequency is assumed as constant. Accordingly, a power resistor which has a large size and high price would be required, which prevents the reduction of the power invertor in size, cost and loss. Fourthly, since a capacitor having a high capacitance will deteriorate the operation speed of the switching element, it will make it impossible to conduct pulse width modulation control (PMW) with a high resolution.
Another example of the prior art surge voltage suppressing means is disclosed in JP-A-6-326579. Since a surge voltage which is generated at the drain terminal of a MOS transistor is clamped at a given voltage in present means, a series-connected circuit of a zener-diode and a reverse blocking diode is connected between the gate and the drain of the MOS transistor. When a current flowing through a load is cut off by driving the MOSFET into an non-conductive state, a surge voltage is generated on the drain terminal due to the parasitic inductance. When the surge voltage will exceed the sum of the breakdown voltage and the forward voltage of the zener diode, the voltage on the gate of the MOS transistor will become higher, so that the MOS transistor is turned on to absorb the surge voltage. This circuit is known as so-called xe2x80x9cactive clamping circuitxe2x80x9d. The active clamping circuit overcomes the disadvantage of the above-mentioned snubber circuit and has an advantage that the clamped voltage is kept constant independently of the magnitude of the parasitic inductance and the cut-off current.
However, if the active clamping circuit is applied to a MOS transistor having a higher switching speed than that of IGBT, a problem may occur in connection with the surge voltage clamping characteristics in the prior art circuit configuration.
A first problem is that the peak of the surge voltage will exceed a desired clamp voltage. Accordingly, it is necessary to use a switching element having a margin against this clamp voltage and having a higher maximum rated voltage. Since the turn-on resistance of the switching element increases in proportional to the maximum rated voltage, the loss on turning-on increases. Since the switching element having a high maximum rated voltage and a low turn-on resistance has a wider area, it becomes more expensive.
A second problem is voltage oscillation P2 at radio frequencies during the clamping operation and the voltage oscillation at radio frequencies P3 after the completion of the clamping operation (see FIG. 18). Although this oscillation will not cause the breakdown of the switching element due to the surge voltage, there is a risk of causing electromagnetic interference (EMI) noise which may adversely affect to peripheral electronic circuits and devices.
It is an object of the present invention, to solve above-mentioned problems, to provide a power inverter which is capable of suppressing the peak of surge voltage to a lower level even if a switching element has a higher switching speed and of suppressing radio frequency oscillation after the suppression of the surge voltage.
The present inventors have found that the reason why the peak voltage can not be clamped at a desired voltage is that the formation of a negative feedback path between the drain and the gate of an MOS transistor has a time lag when a surge-voltage occurs. The time lag is caused mainly by an increase in the radio frequency impedance due to the parasitic inductance in the negative feedback path and the time lag due to the forward recovery time of the reverse-blocking diode.
The voltage swinging (oscillation) is a loop oscillation which is inherent in the negative feedback control, that is a resonant oscillation caused by the parasitic inductance and parasitic capacitance.
Based upon the above-mentioned finding, a power inverter according to an aspect of the present invention comprises a circuit for canceling an inductive impedance of a negative feedback path as means for speeding up the negative feedback path extending from the drain of a MOS switching element to the gate thereof and a circuit for shortening the forward recovery period of time of a reverse-blocking diode in the negative feedback path. The power inverter further comprises a circuit for preventing the radio frequency oscillation after the suppression of the surge voltage.
Other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the invention taken in conjunction with the accompanying drawings.